The present invention relates generally to semiconductor packaging.
Semiconductor packaging technologies were designed for the known temperature limits of silicon and gallium arsenide (GaAs) technologies which are near the 125xc2x0 C. range. These packages are able to use polymer materials and metal interfaces, such as wire bonds, in this range of operation without sustaining heat damage. Current GTO (gate turn off thyristor) packages are a scaling of known technologies, due to the large size of the silicon devices, but they operate within the same temperature limits of silicon-based operation.
It is calculated that silicon carbide (SiC) devices will be as much as 40 times smaller than present-day silicon devices, and will be 2 to 3 times as hot. SiC devices will create a paradigm shift in the packaging and interconnect technologies, because present packaging technologies will be incapable of operation at the higher temperatures. The reduction in size, along with the increase in the voltage handling capability of the SiC material and the much higher temperature range of operation (near 350xc2x0 C.) demands a fundamental change in the packaging concepts for SiC devices.
Commonly-assigned Wojnarowski, U.S. Pat. Nos. 5,672,546 and 5,949,133 describe a fabrication process that both interconnects semiconductor die efficiently and is capable of withstanding continuous high temperature environments by using a temporary laminate structure with a removable polymer layer to facilitate deposition of metallization patterns and later removing the polymer layer. The packaging approach of these patents is capable of operation for temperatures in excess of 400xc2x0 C. and can be used to facilitate interfacing of high temperature packaging materials, including metals and ceramics, in a low inductance manner, and of customizing of the coefficients of thermal expansion (CTE) to match the CTE of SiC. The techniques described in these patents are used for high temperature interconnect as well as a high temperature die attach.
SiC devices have several different die sizes and have different power density efficiencies that vary with respect to the device size. FIG. 1, for example, illustrates arrays of small 12, medium 13, and large 14 SiC devices 11 mounted for interconnection on a single substrate, die or wafer. Currently, however, multiple smaller SiC devices 11 on a single die are more efficient than larger SiC devices 11 made on the same die in terms of current handling capacity per area, and it is often desirable to build the approximate functionality of larger devices out of an interconnected plurality of smaller devices on a common substrate die size.
In addition, SiC micro pipe defects currently make it difficult to reliably produce large area devices with good yield and regularity. That is, the fabrication of smaller SiC devices yields a much higher percentage of operational (non-defective) devices than does the fabrication of larger SiC devices. Even the fabrication of smaller SiC devices still yields a significant percentage (approximately 10% to 40%) of defective devices. So, for example, a single pipe defect in a wafer including one large device 14 destroys the whole die or wafer, whereas a similar defect in a small device 12 on a wafer including a plurality of small devices destroys only that device, but saves the overall die and the remaining devices on that die or wafer.
Among non-defective devices, there are also variations in effectiveness. For example, two xe2x80x9ctheoreticallyxe2x80x9d identical SiC devices 11 may actually vary somewhat with respect to current passing through the devices for a fixed applied voltage. Finally, there are no apparent technology solutions expected to the problem of SiC micro pipe defects, at least over the short term. So any near-term use of SiC technology must have built in from the start, and be based on, the recognition that a fair percentage of the SiC devices 11 produced on any given die, wafer or similar amalgamation of SiC devices 11 will be defective, and that among the working SiC devices 11, operational variations are to be expected.
SiC devices are made by wafer diffusion and/or implantation technology steps. As stated above, due to the immaturity of SiC materials technology and in particular the presence of micro pipe defects, the characteristics of the devices, die and wafers vary from lot to lot, and the devices within a given lot also vary with reference to the current passed through the device, with a fixed voltage applied. Thus xe2x80x9ccurrent hoggingxe2x80x9d similar to that encountered for silicon technology develops wherein some devices run much hotter than associated die, causing hot spots and reliability concerns. The differential current carrying capacity from device to device by lot and wafer, and the resulting temperature variations, cause a long-term reliability concern and pose a serious design and fabrication problem. Die that fail because of shorting cannot be easily dropped from the array of parallel devices, thus destroying the entire array. Additionally, arrays of die or whole wafers of die have intrinsic heat at their centers which is higher than the heat around their edges. Thus, a method is needed to lower the power in critical areas to achieve a uniform heat and reliability model.
Therefore, a novel concept is needed to manage the current to balance the die to die matching problems and deal with the non-working die that are to be expected in any given production lot.
Thus, it is desirable to achieve a method of gang paralleling high temperature devices such as SiC semiconductor devices and associated technologies that will work at and above the 300xc2x0 C. SiC operating temperature range.
It is also desirable to enable a shorted device to be removed from an active die or wafer array without having to destroy the whole array, preferable in a self-eliminating way requiring no human intervention.
It is also desirable to enable die, small and larger arrays of die, whole wafers, and portions of wafers to be used within a common technology framework. In particular, it is desirable for die from different wafers with different characteristics and sizes to be used within a common package.
Briefly, according to one embodiment of the present invention, a method for interconnecting high-temperature silicon carbide (SiC) SiC devices includes: empirically measuring operational characteristics of a plurality of said SiC devices to be interconnected. These operational characteristics comprise SiC devices which are measured to be non-working and SiC devices which are measured to be working. The method further includes characterizing these operational characteristics in an operational characteristics map; designing interconnection paths between and among the SiC devices that are characterized to be working by the operational characteristics map; and excluding from these interconnection paths SiC devices that are characterized to be non-working by the operational characteristics map.
Also disclosed is an interconnected die or wafer array apparatus produced by this method.